1. Field of the Invention
The invention relates generally to the field of communication systems. More particularly, the invention relates to synchronization of communication systems. Specifically, a preferred implementation of the invention relates to a cascaded digital phase locked loop (PLL) based clock design.
2. Discussion of the Related Art
In telecommunications, there has always been a need to provide a distributed synchronization infrastructure to ensure the each node of the network operates within a controlled frequency tolerance. For example, prior to the use of digital communications, Frequency Division Multiple Access (FDMA) systems were used to gain efficient use of the communications channels between nodes. In these FDMA systems, voice channels are aggregated together in to a contiguous group of frequencies and assigned a particular channel frequency for transport. To prevent interference as groups from various originating nodes are multiplexed together, it is critical that channel assignments have tightly controlled frequency tolerance. Thus, each node must be provided with synchronization to control its frequency error. FDMA based systems have been replaced to a large extent by digital time division systems, but FDMA continues to be employed in mobile systems, and increasingly in wave division fiber optical systems.
Time Division Multiple Access (TDMA) digital communications systems have replaced FDMA as the current backbone for telecommunications. In these systems, a particular user's traffic is assigned a given timeslot that repeats at a given rate. The resulting traffic is a fixed bit rate determined by the originating node. To prevent data corruption problems the average rate of all channels should be the same for all nodes. Small discrepancies can be managed at a switching node by producing slips in the data. A slip is either a deletion or repetition of a group of bits to force rate equality. For example, if a switch clock is running fast with respect to an incoming user channel, then the outgoing line will have occasional duplications of data (typically bytes) to fill in the timing gaps.
To control the slip rates of services, multiple standards organizations have established both interface and functional synchronization standards. One key aspect of these standards is the use of various levels or strata of clocks. The stratification of clocks is used in conjunction with constraints on distribution topologies. For example, in North America, four basic stratum levels have been established for clocks. A stratum 1 clock is the highest performance clock and a stratum 4 is the lowest performance clock. There is a vast difference in both cost and performance encompassed in the stratum levels. In general, the stratum levels are loosely aligned with technology breakpoints for oscillators. A stratum clock's required functions encompass a number of factors beyond the performance of the local oscillator itself, but oscillator technology should be the dominant cost/performance driver in a well-designed stratum clock. Thus, stratum 1 requires the use of a primary atomic clock such a cesium tube standard to provide better than 1*10−11 autonomous accuracy. There is also the option to use a primary reference clock (PRC) in place of a stratum 1 clock. This equipment receives an external radio based precise timing source such as GPS or LORAN-C to discipline a non-stratum 1 oscillator to effectively performed at a verified stratum 1 level. A PRC must meet stringent performance requirements such as Telcordia GR-2830. Moving down the stratum levels, secondary atomic clocks such as rubidium cells and high performance Oven Controlled Crystal Oscillators (OCXO) such as SC cut double ovens may be used in stratum 2 clocks. Lower cost single oven AT cut OCXOs and non oven based Temperature Compensated Crystal Oscillators (TCXOs) can be employed in stratum 3 and stratum 4 based clocks.
To achieve a cost effective synchronization infrastructure, it is highly desirable to utilize lower level stratum 3 and 4 clocks as embedded clocks in telecommunication systems. Unfortunately, these lower level clocks are much more vulnerable to external influences which can degrade performance.
Near et al.[1](Method for Synchronizing Interconnected Digital Equipment, U.S. Pat. No. 5,068,877) teaches that lower level stratum clocks can produce significant time error residuals and even propagate transmission errors as a result of normal daily transmission error activities on a synchronization reference input. The core problem underlying accumulated time error residuals is that frequency rather than time is distributed in networks. The delay in the path is not known. If as a result of a transmission error burst, a receive stratum clock switches to a backup reference, there is always some uncertainly as to the new phase position to establish. This effect is aggravated by phase noise on the reference and the local oscillator, as well as measurement resolution. A similar effect can be produced by a change in the effective path even without an active switch of a reference. These transient errors are classified as either rearrangement or phase build-out transients.
The problem of propagated transmission errors is related to the slew rate and amplitude of an individual phase transient event. In higher speed digital system, the high frequency content of the phase transient is sufficient to corrupt the eye pattern and generate transmission errors. Since all outgoing transmission links can be impacted, this error mechanism can result in an overall error multiplication. Therefore, an emerging need for improved transient management is in conjunction with high speed digital systems. Another emerging need for improved transient management is in conjunction with the use of network inputs for wireless applications to generate low phase noise high frequency carriers.
These phase transient problems are typically managed in two ways. The first tool used in managing transients is that functional standards have been established, such as Telcordia GR1244[3], to set limits on these transients. However, the limits are lax, to reduce the cost impact on embedded clocks. The second tool used in managing transients is in utilizing an optimized synchronization distribution network design such as disclosed in Near et al.[1], While careful attention to network design can reduce the overall degradation level, a more significant improvement can be afforded by designing low cost stratum clocks with significantly reduced transient errors.
Current methodologies for phase build-out can be categorized as either phase jamming or phase averaging approaches. The most simple form of phase build-out is a phase jamming technique. In phase jamming, typically the local oscillator divider is jammed to the same count value as the input reference divider, which, in principle, can align the two input signals to the phase detector to within one local oscillator clock period. Although this is a common technique used in clock design, it has severe limitations. Since the jam is performed synchronously with an input reference edge, the residual phase bias is completely dependent on incoming high frequency phase noise (termed jitter). Since peak-to-peak input jitter can be an order of magnitude greater than the required maximum phase transient, the phase jamming does not ensure compliance to standards and can produce severe transient problems.
To counter-act some of the limitation of phase jamming, phase averaging approaches can be employed. Wolf[2](Clock Generator and Synchronizing Method, U.S. Pat. No. 6,181,175) teaches a phase averaging technique. The basic premise is that after an abnormal phase step is detected, the phase locked loop (PLL) update can be temporarily suspended. During this suspension period, an average of the phase error can be obtained. This average phase error can subsequently be used as compensation during locked operation of the PLL by subtracting this bias from all input phase error measurements.
This method of averaging does reduce the impact of input phase jitter on measuring and attempts to minimize the impact of an input phase transient. However, it has several significant limitations.
First, the approach used to detect an input transient does not include any explicit method to filter jitter. Without suppression of jitter, the detection mechanism is subject to errors. If the detection threshold is set too low, then normal network jitter can produce spurious phase step corrections. This activity will produce both a random walk phase noise and a residual frequency bias. On the other hand, if the threshold is set high to eliminate spurious corrections, then the actual input phase steps will go undetected.
Second, the method requires suspension of the update of the control loop while the phase average is being determined. During the suspension of the control loop update, the local oscillator is free to drift from the optimal phase position. The phase error accumulate during the suspension period is not compensated and is a source of both random walk phase noise and residual frequency bias. The suspension problem is most notable during input reference re-arrangement. If the phase build-out methodology provides for a continuous filtered measurements of multiple input references, then a reference switch can be performed with instantaneous phase build-out.
Heretofore, the requirements of providing a clock designed to perform phase-build-out without the limitations of the existing methods referred to above has not been fully met. What is needed is a solution that addresses these requirements.